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TTTC's Electronic Broadcasting Service |
The 15th IEEE Workshop on Silicon Errors in Logic System Effects
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CALL FOR PAPERS
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The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high-performance applications. The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome. We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Portland, Oregon on June 24 – 27, 2019. Key areas of interest include (but are not limited to):
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Additional information and guidelines for submission are available at the conference website. Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop. |
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| Additional Information | |
You can contact the conference organizers through the conference website at: https://www.selse.org/index.php/contact-us/ |
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| Committee | |
General Co-Chair
General Co-chair Emeritus
Program Co-Chair:
Local Arrangements Chair:
Finance Co-Chair:
Registrations Chair
Publicity Co-Chair
Bay Area Industry Liaison
Web Chair
Advisor to the Committee
Steering Committee
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| For more information, visit us on the web at: https://www.selse.org/ |
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The 15th IEEE Workshop on Silicon Errors in Logic – System Effects is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
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IEEE
Computer Society-Test Technology Technical Council |
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